A non-volatile semiconductor memory device is known as an electrically erasable read only memory device provided with a plurality of floating gate avalanche injection MOS transistors arranged in matrix for forming a memory cell array. Such a floating gate avalanche injection MOS transistor has a double gate structure consisting of a floating gate and a control gate. A typical example of the floating gate avalanche injection MOS transistor is illustrated in FIG. 1 of the drawings and fabricated on a p-type semiconductor substrate 1. The floating gate avalanche injection MOS transistor has n-channel type source and drain regions 2 and 3 spaced from each other by a channel forming region, a floating gate 4 located over the channel forming region and a control gate 5 provided over the floating gate 4, and both of the floating gate 4 and the control gate 5 are wrapped into an insulating film 6. The floating gate avalanche injection MOS transistor thus arranged is usually symbolized as illustrated in FIG. 2, and a data bit of "0" level is memorized into the floating gate avalanche injection MOS transistor by producing an avalanche breakdown around the drain region 3 with application of a relatively high voltage level of about 12.5 volts to both of the drain region 3 and the control gate 6. With the injected floating gate, the floating gate avalanche injection MOS transistor is referred to as "write-in state". When the avalanche breakdown is produced around the drain region 3, hot electrons are injected into the floating gate 4, and, accordingly, the threshold voltage is shifted to a relatively high voltage level as indicated by plots A in FIG. 3. However, if no hot electrons are injected into the floating gate 4 for memorizing a data bit of "1" level ( which is referred to as "non write-in state") the threshold voltage remains in a relatively low voltage level of about 2 volts as indicated by plots B in FIG. 3. In this manner, the floating gate avalanche injection MOS transistor memorizes the data bit by using the difference in the threshold voltage level between the electron injected state and the non-injected state.
Turning to FIG. 4 of the drawings, there is shown the circuit arrangement of a non-volatile semiconductor memory device which has a memory cell array 11 formed by using memory cells MC11 to MCmn. Each of the memory cells MC11 to MCmn is formed by the floating gate avalanche injection MOS transistor. The memory cells in each row are coupled between respective digit lines D1 to Dn and a ground terminal Vg, and each word line W1, W2 or Wn is shared by the control gates of these memory cells in each row. With a row address signal, a row address decoder circuit 12 activates one of the word lines W1 to Wn and, accordingly, the memory cells in the selected row. Each of the digit lines D1 to Dn is coupled at one end thereof to each gate transistor Y1, Y2 or Yn of the n-channel type the gate electrode of which is coupled to a column decoder circuit 13. The column decoder circuit 13 is responsive to a column address signal and activates one of the gate transistors Y1 to Yn, so that only one data bit is transferred from one of the digit lines D1 to Dn to a sense circuit 14. Parasitic capacitance C1, C2, . . . , and Cn are coupled to the digit lines D1, D2, . . . , and Dn, respectively.
The prior art sense circuit 14 incorporated in the non-volatile semiconductor memory device comprises a series combination of an n-channel type MOS field effect transistor 15 and a p-channel type MOS field effect transistor 16 coupled between an input node 17 of the sense circuit 14 and a source of positive voltage level Vc, and an inverter circuit 18 coupled between the input node 17 and the gate electrode of the n-channel type MOS field effect transistor 15, and the drain electrode of the p-channel type field effect transistor 16 is coupled to the gate electrode thereof serving as an output node 19 of the sense circuit 14. The sense circuit 14 thus arranged is operative to detect a variation in voltage level at the input node 17 on the basis of the level of the data bit and transfers the data bit to the output node 19. The output node 19 is coupled to a differential amplifier circuit 20 which largely comprises a series combination of a p-channel type field effect transistor 21 and an n-channel type field effect transistor 22 coupled between the source of positive voltage level Vc and the ground terminal Vg, and a series combination of a p-channel type field effect transistor 23 and an n-channel type field effect transistor 24 also coupled between the source of positive voltage level Vc and the ground terminal Vg. Both n-channel type field effect transistors 22 and 24 form in combination a current mirror circuit, so that the data bit is rapidly amplified in voltage level and supplied to an output node 25 provided between the p-channel type field effect transistor 21 and the n-channel type field effect transistor 22.
Description is hereinunder made for circuit behaviors on the assumption that the memory cell MC11 is accessed from the outside thereof. The waveforms of the essential signals are shown in FIG. 5. In a ready for access stage T1, the ground voltage level is supplied to the gate electrode of the gate transistor Y1, the word line W1, the gate electrode of the n-channel type field effect transistor 15, the output node 25 of the differential amplifier circuit 20, and the digit line D1, however, the output node 19 of the sense circuit 14 remains in a positive voltage level slightly lower than the positive voltage level Vc. When the access to the memory cell MC11 starts with the row address signal and the column address signal, the row address decoder circuit 12 allows the word line W1 to go up to the positive voltage level Vc, and the column address decoder circuit 13 provides the positive voltage level Vc to the gate electrode of the gate transistor Y1 for causing the gate transistor Y1 to turn on. Then, the gate electrode of the n-channel type field effect transistor 15 is higher in voltage level than the source node thereof by virtue of the inverter circuit 18, and, for this reason, the n-channel type field effect transistor 15 turns on. As a result, a current path is established from the source of positive voltage level Vc through the series combination of the p-channel type field effect transistor 16 and the n-channel type field effect transistor 15 and the gate transistor Y1 to the digit line D1. If the data bit of "0" level is the memory cell MC11, no channel is produced in the memory cell MC11. Then, the current is consumed to charge up the parasitic capacitance C1 coupled to the digit line D1, and, for this reason, the digit line D1 is gradually increased in voltage level over a relatively long time period T2 and, finally, reaches a positive voltage level. When the digit line D1 reaches the positive high voltage level, the inverter circuit 18 produces a high voltage level with respect to the source electrode of the n-channel type field effect transistor 15, so that the n-channel type field effect transistor 15 turns off. When the n-channel type field effect transistor 15 is turned off, the current is used for increasing the voltage level of the output node 19. With the high voltage level at the output node 19, the p-channel type field effect transistor 21 turns off, so that the output node of the differential amplifier circuit 20 is recovered to the ground level. In this manner, the read-out data bit is fixed to the low voltage level, and, for this reason, the memory cell MC11 is detected to be in the write-in state in a time period T3. However, if the data bit of "1" is memorized in the memory cell MC11, the current flows into the ground terminal, so that the n-channel type field effect transistor 15 remains in the on state, thereby causing the output node 19 to stay in the low voltage level. This results in that the p-channel type field effect transistor 21 is turned on to maintain the output node 25 in the high voltage level. Then, the memory cell MC11 is detected to be in the non write-in state.
A problem is encountered in the prior art sense circuit 14 in the relatively long access time. For decreasing the access time, the n-channel type field effect transistor 15 may be formed by a field effect transistor with a broader gate electrode. When the gate electrode is increased in gate width, the field effect transistor has a large current driving capability, so that the parasitic capacitance C1 would be rapidly charged up. However, if the field effect transistor 15 has a broader gate electrode, the sense circuit 14 is more sensitive to noises riding on the ground voltage level. This results in that an error data bit tends to be transiently delivered to the outside.
In detail and referring to FIG. 6, assuming now that the inverter circuit 18 has a threshold voltage Vth18 of 1 volt on an input voltage to output voltage characteristic line 31a and that the n-channel type field effect transistor 15 also has a threshold voltage Vth15 of 1 volt in which the back gate biasing effect is taken into account, the n-channel type field effect transistor 15 turns off at the gate voltage level V15 due to the voltage level on the digit line D1 increased in voltage level if the memory cell MC11 is in the write-in state. The gate voltage level V15.sub.OFF causing the field effect transistor 15 to turn off is indicated by an intersecting point 33a of the characteristic line 31a and a linear line 32a. The linear line 32a is representative of the gate voltage level V15 or the total voltage in terms of the voltage level V17 at the input node 17 and calculated as: EQU V15=V17+Vth15
However, if the non write-in state has been established in the memory cell MC11, a current passes through the n-channel type field effect transistor 15 for inverting the voltage level at the output node 25, and the voltage level V15.sub.ON for allowing the current to flow is calculated as EQU V15.sub.ON =V17+Vth15+2 volt
The voltage level V15.sub.ON allowing the current to flow is represented by an intersecting point 33c of the characteristic line 31a and a linear line 32c. However, if the n-channel type field effect transistor 15 is formed by a field effect transistor with a broader gate electrode, the current for inverting the voltage level at the output node 25 takes place at the gate voltage level V15.sub.ON' which is lower than that indicated by the intersecting point 33c. An intersecting point 33b representative of the voltage level V15.sub.ON ' is by way of example calculated as: EQU V15.sub.ON' =V18+Vth15+1 volt
In this situation, if noises takes place in the ground voltage level Vg, the input voltage to output voltage characteristics of the inverter circuit 18 is shifted from the line 31a to a line 31 b. The gate voltage level V15.sub.0FF allowing the n-channel type field effect transistor 15 to stay in the stable state is accordingly moved from the intersecting point 33a to an intersecting point 34. The intersecting point 34 is higher in voltage level than the intersecting point 33b, so that the output node 25 transiently indicates the non write-in state even though the memory cell MC11 has been established in the write-in state. The field effect transistor with the broader gate electrode is thus liable to cause the output node 25 to indicate the opposite state to the accesses memory cell. Then, there is a trade-off between the rapid read-out operation and the reliability of the data bit read out through the field effect transistor 15 of the broader gate electrode.